Field of the Invention
The present invention relates to a method for fabricating an SOI (Silicon On Insulator) wafer for low-impedance high-voltage semiconductor components.
Dielectrically isolated (DI) epitaxial wafers are desirable for a variety of semiconductor components in order to ensure reliable insulation of adjacent components. Single-chip converters are one example thereof.
DI epitaxial wafers have been obtainable heretofore with a thickness of about 20 .mu.m. However, epitaxial wafers which have a thickness exceeding 20 .mu.m and, moreover, are dielectrically isolated would be advantageous for a wide variety of application purposes such as, by way of example, for obtaining a particularly high dielectric strength. Such DI epitaxial wafers are SOI wafers, for example, in which one or more epitaxial layers are applied on a substrate.